1. Field of the Invention
The present invention relates generally to parallel-to-serial conversion and, more particularly, to parallel-to-serial conversion in high speed memory devices.
2. Description of the Related Art
This section is intended to introduce the reader to various aspects of art which may be related to various aspects of the present invention which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Semiconductor memory devices such as synchronous dynamic random access memory (SDRAM) devices are widely used in computers and electronic systems. An SDRAM device generally includes a memory array comprising a large number of memory cells each configured to store data. During a memory read operation, data from the memory cells is accessed and output to a data pad (DQPAD) for processing and use by external devices. The operation of the SDRAM is generally based on a common clock signal.
As will be appreciated, there are a number of different types of SDRAM devices. Early generation SDRAM devices are generally configured such that data from the memory cells may be accessed and one bit of data may be output to the DQPAD on every clock cycle. Demands for higher processing speeds led to the development of double data rate (DDR) SDRAM devices. DDR SDRAM devices generally allow for two bits of data to be accessed and output to the DQPAD on every clock cycle. To achieve this, DDR SDRAM devices commonly clock data out to the DQPAD on every rising and every failing edge of the clock signal. DDR SDRAMS generally allow for data to be transferred from the memory device at a clock rate in the range of 200 to 550 MHz.
The next generation of SDRAMS include DDR2 SDRAMS. The advantage of DDR2 over DDR SDRAMS is its ability to run at even higher clock speeds due to an improved electrical interface. With a clock frequency of 100 MHz, an SDRAM will transfer data on every rising edge of the clock pulse, thus achieving an effective 100 MHz transfer rate. Like DDR, DDR2 will transfer data on every rising and falling edge of the clock, achieving an effective rate of 200 MHz with the same clock frequency. DDR2's clock frequency is further boosted by an improved electrical interface running twice as fast as the memory clock, on-die termination, pre-fetch buffers and off-chip drivers. Thus, DDR2 devices have a data transfer rate in the range of 500-667 MHZ. With the next generation of SDRAMs being developed to facilitate data transfer rates in the range of 800-1067 MHZ (DDR3), internal transfer of data within the memory device becomes increasingly difficult to manage.
To facilitate the ever increasing processing speeds, data is often split onto parallel data buses within the memory devices such that concurrent processing may be utilized. While concurrency does improve accessing and processing speeds, eventually, the parallel data is serialized in order to pipeline the output data in a serial manner. Due to the ever increasing transfer rates of the memory devices, parallel-to-serial conversion for serially pipelining the data output from the memory device becomes increasingly challenging.
The present invention may address one or more of the problems set forth above.